Asynchronous Microprocessor the Clockless Future

distributing the clock signal on the chip in a manner such that it reaches all sinks at exactly the same point in time, a huge effort must be made. For example, the H-clock tree or B-Tree can achieve a low clock skew at the cost of many additional wires, which increases the chip size, cost and energy dissipation due to the capacitances that are created by thousands of parallel wires in the clock tree. The speeding up of a synchronous processor is possible by optimising the critical path. Either its elements have to be optimised or it has to be split up so that it takes more than one clock cycle to compute the final result. The latter way introduces a new overhead. But, in asynchronous processors, there are several starting points: Each optimised element can speed up the processor, so there is no need to make effort to optimise only rarely used parts. Instead, only frequently used parts are optimised to increase the average speed of the entire processor. If changes in combinatory logic elements (like increase in temperature and lowered supply voltage) slow down the operational performance of the processor, the clock of the synchronous chip has to be regulated actively to keep the system in a valid state. But, asynchronous systems can implicitly adapt to these variations, which means that they always run at the maximum speed possible. Another implication of the automatic performance adaptation is that an asynchronous system always World’s first flexible 8-bit asynchronous microprocessor developed by Seiko Epson using low-temperature polysilicon thin-film transistors on a plastic substrate. With energy consumption reduced by 70 per cent compared to the synchronous microprocessors now in everyday use, Epson is now researching potential applications for its invention (courtesy: http://global.epson.com)